BQ4285EP【PDF 29/31 页】IC RTC W/114X8 NVSRAM 24-DIP

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Alarm Interrupt

The alarm interrupt request is valid in battery-backup

mode, providing a “wake-up” capability. During each up-

date cycle, the RTC compares the hours, minutes, and

seconds bytes with the three corresponding alarm bytes.

If a match of all bytes is found, the alarm interrupt

event flag bit, AF in register C, is set to 1. If the alarm

event is enabled, an interrupt request is generated.

An alarm byte may be removed from the comparison by

setting it to a “don’t care” state. An alarm byte is set to a

“don’t care” state by writinga1toeachofitstwo most-

significant bits. A “don’t care” state may be used to select

the frequency of alarm interrupt events as follows:

If none of the three alarm bytes is “don’t care,” the

frequency is once per day, when hours, minutes, and

seconds match.

If only the hour alarm byte is “don’t care,” the

frequency is once per hour, when minutes and

seconds match.

If only the hour and minute alarm bytes are “don’t care,”

the frequency is once per minute, when seconds match.

If the hour, minute, and second alarm bytes are

“don’t care,” the frequency is once per second.

Update Cycle Interrupt

The update cycle ended flag bit (UF) in register C is set to

a 1 at the end of an update cycle. If the update interrupt

enable bit (UIE) of register B is 1, and the update transfer

inhibit bit (UTI) in register B is 0, then an interrupt re-

quest is generated at the end of each update cycle.

Accessing RTC bytes

Time and calendar bytes read during an update cycle

may be in error. Three methods to access the time and

calendar bytes without ambiguity are:

Enable the update interrupt event to generate

interrupt requests at the end of the update cycle.

The interrupt handler has a maximum of 999ms to

access the clock bytes before the next update cycle

begins (see Figure 3).

Poll the update-in-progress bit (UIP) in register A. If

UIP = 0, the polling routine has a minimum of tBUC

time to access the clock bytes (see Figure 3).

Use

the

periodic

interrupt

event

generate

interrupt requests every tPI time, such that UIP = 1

always occurs between the periodic interrupts. The

interrupt handler will have a minimum of

tPI/2 +

tBUC time to access the clock bytes (see Figure 3).

Oscillator Control

When power is first applied to the bq4285E/L and VCC is

above VPFD, the internal oscillator and frequency divider

are turned on by writing a 010 pattern to bits 4 through 6

of register A. A pattern of 011 behaves as 010 but addi-

tionally transforms register C into a read/write register.

This allows the 32.768kHz output on the square wave pin

to be turned on. A pattern of 11X turns the oscillator on,

but keeps the frequency divider disabled. Any other pat-

tern to these bits keeps the oscillator off.

bq4285E/L

Figure 3. Update-Ended/Periodic Interrupt Relationship

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